Renesas Electronics 9DB102BGLF Clock Buffer 20-Pin TSSOP
- RS stock no.:
- 254-4986
- Mfr. Part No.:
- 9DB102BGLF
- Manufacturer:
- Renesas Electronics
Bulk discount available
Subtotal (1 tube of 74 units)*
R 2 507,86
(exc. VAT)
R 2 883,78
(inc. VAT)
FREE delivery for orders over R 1,500.00
In Stock
- Plus 222 unit(s) shipping from 29 December 2025
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tube* |
|---|---|---|
| 74 - 222 | R 33.89 | R 2,507.86 |
| 296 - 444 | R 33.042 | R 2,445.11 |
| 518 + | R 32.051 | R 2,371.77 |
*price indicative
- RS stock no.:
- 254-4986
- Mfr. Part No.:
- 9DB102BGLF
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Maximum Supply Current | 100 mA | |
| Maximum Input Frequency | 101MHz | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Maximum Supply Current 100 mA | ||
Maximum Input Frequency 101MHz | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics zero-delay buffer supports PCI express clocking requirements. it is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL band width to maximize performance in systems with or without spread-spectrum clocking.
CLKREQ pin for outputs 1 and 4/output enable for express card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
Spread spectrum compatible/tracks spreading input clock for low EMI
SMBus interface/unused outputs can be disabled
Industrial temperature range available
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
Spread spectrum compatible/tracks spreading input clock for low EMI
SMBus interface/unused outputs can be disabled
Industrial temperature range available
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