Renesas Electronics 9DB102BGILF, LVDS Buffer Dual TTL Buffer, 20-Pin TSSOP
- RS stock no.:
- 217-7929
- Mfr. Part No.:
- 9DB102BGILF
- Manufacturer:
- Renesas Electronics
Bulk discount available
Subtotal (1 pack of 5 units)*
R 422,93
(exc. VAT)
R 486,37
(inc. VAT)
FREE delivery for orders over R 1,500.00
Temporarily out of stock
- 120 left, ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 5 - 5 | R 84.586 | R 422.93 |
| 10 - 20 | R 82.472 | R 412.36 |
| 25 - 95 | R 79.998 | R 399.99 |
| 100 - 245 | R 76.798 | R 383.99 |
| 250 + | R 73.726 | R 368.63 |
*price indicative
- RS stock no.:
- 217-7929
- Mfr. Part No.:
- 9DB102BGILF
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Drivers | 2 | |
| Input Type | TTL | |
| Output Type | Buffer | |
| Number of Elements per Chip | 2 | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Drivers 2 | ||
Input Type TTL | ||
Output Type Buffer | ||
Number of Elements per Chip 2 | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.
2 - 0.7 V HCSL differential output pairs
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
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