Nexperia 74AUP2G08DC,125, Dual 2-Input AND Schmitt Trigger Logic Gate, 8-Pin VSSOP
- RS stock no.:
- 153-2935
- Mfr. Part No.:
- 74AUP2G08DC,125
- Manufacturer:
- Nexperia
Bulk discount available
Subtotal (1 pack of 25 units)*
R 126,175
(exc. VAT)
R 145,10
(inc. VAT)
Stock information currently inaccessible
Units | Per unit | Per Pack* |
|---|---|---|
| 25 - 225 | R 5.047 | R 126.18 |
| 250 - 600 | R 4.921 | R 123.03 |
| 625 - 1225 | R 4.774 | R 119.35 |
| 1250 - 2475 | R 4.583 | R 114.58 |
| 2500 + | R 4.40 | R 110.00 |
*price indicative
- RS stock no.:
- 153-2935
- Mfr. Part No.:
- 74AUP2G08DC,125
- Manufacturer:
- Nexperia
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Function | AND | |
| Mounting Type | Surface Mount | |
| Number of Elements | 2 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | Yes | |
| Package Type | VSSOP | |
| Pin Count | 8 | |
| Logic Family | AUP | |
| Input Type | CMOS | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Maximum High Level Output Current | -4mA | |
| Maximum Propagation Delay Time @ Maximum CL | 24 @ 30 pF | |
| Minimum Operating Supply Voltage | 0.8 V | |
| Maximum Low Level Output Current | 4mA | |
| Propagation Delay Test Condition | 30pF | |
| Length | 2.1mm | |
| Height | 0.85mm | |
| Width | 2.4mm | |
| Minimum Operating Temperature | -40 °C | |
| Dimensions | 2.1 x 2.4 x 0.85mm | |
| Maximum Operating Temperature | +125 °C | |
| Output Type | ECL | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Function AND | ||
Mounting Type Surface Mount | ||
Number of Elements 2 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input Yes | ||
Package Type VSSOP | ||
Pin Count 8 | ||
Logic Family AUP | ||
Input Type CMOS | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum High Level Output Current -4mA | ||
Maximum Propagation Delay Time @ Maximum CL 24 @ 30 pF | ||
Minimum Operating Supply Voltage 0.8 V | ||
Maximum Low Level Output Current 4mA | ||
Propagation Delay Test Condition 30pF | ||
Length 2.1mm | ||
Height 0.85mm | ||
Width 2.4mm | ||
Minimum Operating Temperature -40 °C | ||
Dimensions 2.1 x 2.4 x 0.85mm | ||
Maximum Operating Temperature +125 °C | ||
Output Type ECL | ||
Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption, ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
High noise immunity
Low static power consumption, ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
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