Renesas Electronics 2305A-1DCG8 Clock Buffer 8-Pin SOIC
- RS stock no.:
- 264-3451
- Mfr. Part No.:
- 2305A-1DCG8
- Manufacturer:
- Renesas Electronics
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Bulk discount available
Subtotal (1 pack of 5 units)*
R 58,89
(exc. VAT)
R 67,725
(inc. VAT)
Add 135 units to get free delivery
In Stock
- 3,000 unit(s) ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 5 - 45 | R 11.778 | R 58.89 |
| 50 - 95 | R 11.484 | R 57.42 |
| 100 - 245 | R 11.14 | R 55.70 |
| 250 - 995 | R 10.694 | R 53.47 |
| 1000 + | R 10.266 | R 51.33 |
*price indicative
- RS stock no.:
- 264-3451
- Mfr. Part No.:
- 2305A-1DCG8
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | IDT2305A | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series IDT2305A | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
The Renesas Electronics high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133 MHz.
Phase-lock loop clock distribution
Distributes one clock input to one bank of five outputs
Power down mode
Available in SOIC package
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