Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP
- RS stock no.:
- 263-7981
- Mfr. Part No.:
- 9DB106BGLF
- Manufacturer:
- Renesas Electronics
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Bulk discount available
View bulk pricing optionSubtotal (1 pack of 2 units)*
R 168,25
(exc. VAT)
R 193,488
(inc. VAT)
FREE delivery for orders over R 1,500.00
In Stock
- Plus 80 unit(s) shipping from 01 June 2026
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Units | Per unit | Per Pack* |
|---|---|---|
| 2 - 8 | R 84.125 | R 168.25 |
| 10 - 18 | R 82.02 | R 164.04 |
| 20 - 48 | R 79.56 | R 159.12 |
| 50 - 98 | R 76.38 | R 152.76 |
| 100 + | R 73.325 | R 146.65 |
*price indicative
- RS stock no.:
- 263-7981
- Mfr. Part No.:
- 9DB106BGLF
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 105MHz | |
| Mount Type | Surface | |
| Maximum Propagation Delay Time | 150ps | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Minimum Supply Voltage | 2.7V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Length | 9.7mm | |
| Height | 1mm | |
| Series | 9DB106 REV L | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 105MHz | ||
Mount Type Surface | ||
Maximum Propagation Delay Time 150ps | ||
Package Type TSSOP | ||
Pin Count 28 | ||
Minimum Supply Voltage 2.7V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Length 9.7mm | ||
Height 1mm | ||
Series 9DB106 REV L | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
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