Renesas Electronics 23S05E-1DCG Clock Buffer 8-Pin SOIC
- RS stock no.:
- 263-7885
- Mfr. Part No.:
- 23S05E-1DCG
- Manufacturer:
- Renesas Electronics
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Bulk discount available
Subtotal (1 pack of 5 units)*
R 75,85
(exc. VAT)
R 87,25
(inc. VAT)
FREE delivery for orders over R 1,500.00
Temporarily out of stock
- Shipping from 19 May 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 5 - 5 | R 15.17 | R 75.85 |
| 10 - 20 | R 14.79 | R 73.95 |
| 25 - 45 | R 14.346 | R 71.73 |
| 50 - 90 | R 13.772 | R 68.86 |
| 95 + | R 13.222 | R 66.11 |
*price indicative
- RS stock no.:
- 263-7885
- Mfr. Part No.:
- 23S05E-1DCG
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 200MHz | |
| Maximum Propagation Delay Time | 350ps | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | IDT23S05E | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 200MHz | ||
Maximum Propagation Delay Time 350ps | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series IDT23S05E | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
The Renesas Electronics zero delay clock buffer is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, it enters power down.
Distributes one clock input to one bank of five outputs
Zero input-output delay
Output skew < 250ps
Low jitter <200 ps cycle-to-cycle
No external RC network required
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