Winbond SDRAM 1 GB Surface, 84-Pin 16 bit
- RS stock no.:
- 242-0776
- Mfr. Part No.:
- W971GG6NB25I
- Manufacturer:
- Winbond
Image representative of range
Subtotal (1 tray of 209 units)*
R 13 871,748
(exc. VAT)
R 15 952,552
(inc. VAT)
FREE delivery for orders over R 1,500.00
Temporarily out of stock
- Shipping from 21 August 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tray* |
|---|---|---|
| 209 + | R 66.372 | R 13,871.75 |
*price indicative
- RS stock no.:
- 242-0776
- Mfr. Part No.:
- W971GG6NB25I
- Manufacturer:
- Winbond
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Winbond | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Data Bus Width | 16bit | |
| Address Bus Width | 16bit | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 64M | |
| Mount Type | Surface | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 84 | |
| Maximum Operating Temperature | 95°C | |
| Series | W971GG6NB | |
| Standards/Approvals | RoHS | |
| Height | 0.8mm | |
| Length | 12.6mm | |
| Maximum Supply Voltage | 1.9V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.7V | |
| Select all | ||
|---|---|---|
Brand Winbond | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Data Bus Width 16bit | ||
Address Bus Width 16bit | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 64M | ||
Mount Type Surface | ||
Minimum Operating Temperature -40°C | ||
Pin Count 84 | ||
Maximum Operating Temperature 95°C | ||
Series W971GG6NB | ||
Standards/Approvals RoHS | ||
Height 0.8mm | ||
Length 12.6mm | ||
Maximum Supply Voltage 1.9V | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.7V | ||
The Winbond SDRAM is a 1G bits DDR2 SDRAM which is organized as 8,388,608 words, 8 banks, 16 bits. This device achieves high speed transfer rates for various applications.
Two data transfers per clock cycle
Edge-aligned with read data and centre-aligned with write data
DLL aligns DQ and DQS transitions with clock
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