Nexperia HEF4071BT,653, 4 2-Input OR Gate Logic Gate, 14-Pin SO-14
- RS stock no.:
- 625-398
- Mfr. Part No.:
- HEF4071BT,653
- Manufacturer:
- Nexperia
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Units | Per unit |
|---|---|
| 1 - 24 | R 5.28 |
| 25 + | R 5.15 |
*price indicative
- RS stock no.:
- 625-398
- Mfr. Part No.:
- HEF4071BT,653
- Manufacturer:
- Nexperia
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Function | OR Gate | |
| Product Type | Logic Gate | |
| Mount Type | Surface | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | No | |
| Package Type | SO-14 | |
| Pin Count | 14 | |
| Logic Family | CMOS | |
| Maximum Propagation Delay Time @ CL | 120ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum High Level Output Current | -4.2mA | |
| Maximum Operating Temperature | 125°C | |
| Maximum Supply Voltage | 18V | |
| Width | 3.9 mm | |
| Minimum Supply Voltage | 3V | |
| Length | 8.75mm | |
| Series | HEF4071B | |
| Standards/Approvals | JEDEC JESD 13-B | |
| Maximum Low Level Output Current | 4.2mA | |
| Automotive Standard | No | |
| Output Type | Standard | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Function OR Gate | ||
Product Type Logic Gate | ||
Mount Type Surface | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input No | ||
Package Type SO-14 | ||
Pin Count 14 | ||
Logic Family CMOS | ||
Maximum Propagation Delay Time @ CL 120ns | ||
Minimum Operating Temperature -40°C | ||
Maximum High Level Output Current -4.2mA | ||
Maximum Operating Temperature 125°C | ||
Maximum Supply Voltage 18V | ||
Width 3.9 mm | ||
Minimum Supply Voltage 3V | ||
Length 8.75mm | ||
Series HEF4071B | ||
Standards/Approvals JEDEC JESD 13-B | ||
Maximum Low Level Output Current 4.2mA | ||
Automotive Standard No | ||
Output Type Standard | ||
- COO (Country of Origin):
- CN
The Nexperia Quad 2-input OR gate is designed with input clamp diodes, allowing the use of current limiting resistors to safely interface with input voltages higher than VDD. It provides standard OR logic functionality across four independent gates.
Fully static operation
CMOS low power dissipation
High noise immunity
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
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