Lattice FPGA iCE40 3520 Cells, 80000 bit 440 Blocks, 144-Pin TQFP
- RS stock no.:
- 772-0057P
- Mfr. Part No.:
- iCE40HX4K-TQ144
- Manufacturer:
- Lattice Semiconductor
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Subtotal 10 units (supplied in a tray)*
R 1 379,80
(exc. VAT)
R 1 586,80
(inc. VAT)
Add 11 units to get free delivery
In Stock
- 450 unit(s) ready to ship from another location
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Units | Per unit |
|---|---|
| 10 - 24 | R 137.98 |
| 25 - 49 | R 133.84 |
| 50 - 99 | R 128.49 |
| 100 + | R 123.35 |
*price indicative
- RS stock no.:
- 772-0057P
- Mfr. Part No.:
- iCE40HX4K-TQ144
- Manufacturer:
- Lattice Semiconductor
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Lattice Semiconductor | |
| Product Type | FPGA | |
| Series | iCE40 | |
| Number of Logic Cells | 3520 | |
| Number of Logic Units | 440 | |
| Number of Registers | 3520 | |
| Mount Type | Surface | |
| Package Type | TQFP | |
| Minimum Supply Voltage | 1.14V | |
| Maximum Supply Voltage | 1.26V | |
| Pin Count | 144 | |
| Minimum Operating Temperature | -40°C | |
| Number of I/Os | 96 | |
| Number of RAM Bits | 80000bit | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.45mm | |
| Length | 20mm | |
| Width | 20 mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Lattice Semiconductor | ||
Product Type FPGA | ||
Series iCE40 | ||
Number of Logic Cells 3520 | ||
Number of Logic Units 440 | ||
Number of Registers 3520 | ||
Mount Type Surface | ||
Package Type TQFP | ||
Minimum Supply Voltage 1.14V | ||
Maximum Supply Voltage 1.26V | ||
Pin Count 144 | ||
Minimum Operating Temperature -40°C | ||
Number of I/Os 96 | ||
Number of RAM Bits 80000bit | ||
Maximum Operating Temperature 85°C | ||
Height 1.45mm | ||
Length 20mm | ||
Width 20 mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Field Programmable Gate Arrays, Lattice Semiconductor
An FPGA is a semiconductor device consisting of a Matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a Block of RAM). The FPGA allows changes to be MADE to a design even after the device is soldered into a PCB.