Nexperia 1 Flip Flop IC 74LVC, D Type, 20-Pin TSSOP
- RS stock no.:
- 170-5348P
- Mfr. Part No.:
- 74LVC273PW,118
- Manufacturer:
- Nexperia
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R 6 708,75
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R 7 715,00
(inc. VAT)
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In Stock
- 2,500 unit(s) ready to ship from another location
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Units | Per unit |
|---|---|
| 1250 - 3725 | R 5.367 |
| 3750 - 6225 | R 5.206 |
| 6250 + | R 4.998 |
*price indicative
- RS stock no.:
- 170-5348P
- Mfr. Part No.:
- 74LVC273PW,118
- Manufacturer:
- Nexperia
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 150MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.65V | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 20 | |
| Flip-Flop Type | D Flip-Flop | |
| Minimum Operating Temperature | -40°C | |
| Trigger Type | Positive Edge | |
| Maximum Propagation Delay Time @ CL | 10.5ns | |
| Number of Elements per Chip | 1 | |
| Maximum Operating Temperature | 125°C | |
| Length | 6.6mm | |
| Height | 0.95mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 150MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.65V | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 20 | ||
Flip-Flop Type D Flip-Flop | ||
Minimum Operating Temperature -40°C | ||
Trigger Type Positive Edge | ||
Maximum Propagation Delay Time @ CL 10.5ns | ||
Number of Elements per Chip 1 | ||
Maximum Operating Temperature 125°C | ||
Length 6.6mm | ||
Height 0.95mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and Master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
Related links
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