Toshiba 74HC138D, Decoder, 16-Pin SOIC
- RS stock no.:
- 171-3556
- Mfr. Part No.:
- 74HC138D
- Manufacturer:
- Toshiba
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Bulk discount available
Subtotal (1 pack of 50 units)*
R 336,30
(exc. VAT)
R 386,75
(inc. VAT)
FREE delivery for orders over R 1,500.00
In Stock
- Plus 500 unit(s) shipping from 09 February 2026
- Plus 8,500 unit(s) shipping from 16 February 2026
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Units | Per unit | Per Pack* |
|---|---|---|
| 50 - 450 | R 6.726 | R 336.30 |
| 500 - 2450 | R 6.557 | R 327.85 |
| 2500 - 4950 | R 6.361 | R 318.05 |
| 5000 - 24950 | R 6.106 | R 305.30 |
| 25000 + | R 5.862 | R 293.10 |
*price indicative
- RS stock no.:
- 171-3556
- Mfr. Part No.:
- 74HC138D
- Manufacturer:
- Toshiba
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Product Type | Decoder | |
| Logic Family | 74HC | |
| Logic Function | Decoder | |
| Number of Inputs | 3 | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 16 | |
| Number of Outputs | 34 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Minimum Operating Temperature | 125°C | |
| Maximum Operating Temperature | -40°C | |
| Series | 74HC | |
| Standards/Approvals | No | |
| Length | 10.2mm | |
| Height | 1.75mm | |
| Width | 4 mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Product Type Decoder | ||
Logic Family 74HC | ||
Logic Function Decoder | ||
Number of Inputs 3 | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 16 | ||
Number of Outputs 34 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Minimum Operating Temperature 125°C | ||
Maximum Operating Temperature -40°C | ||
Series 74HC | ||
Standards/Approvals No | ||
Length 10.2mm | ||
Height 1.75mm | ||
Width 4 mm | ||
Automotive Standard No | ||
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and alloutputs go high.G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 16 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V