853S011BGILF, Clock Buffer, 2-Input, 8-Pin SOIC
- RS stock no.:
- 216-6212
- Mfr. Part No.:
- 853S011BGILF
- Manufacturer:
- Renesas Electronics
Bulk discount available
Subtotal (1 pack of 2 units)*
R 200,10
(exc. VAT)
R 230,12
(inc. VAT)
FREE delivery for orders over R 1,500.00
In Stock
- 162 unit(s) ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 2 - 8 | R 100.05 | R 200.10 |
| 10 - 18 | R 97.55 | R 195.10 |
| 20 - 48 | R 94.625 | R 189.25 |
| 50 - 98 | R 90.84 | R 181.68 |
| 100 + | R 87.205 | R 174.41 |
*price indicative
- RS stock no.:
- 216-6212
- Mfr. Part No.:
- 853S011BGILF
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 8 | ||
The Renesas Electronics 853S011B is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011B is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S011B ideal for those clock distribution applications demanding well defined performance and repeatability.
Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)