Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- RS stock no.:
- 216-6206
- Mfr. Part No.:
- 8305AGLF
- Manufacturer:
- Renesas Electronics
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Subtotal (1 pack of 2 units)*
R 308,57
(exc. VAT)
R 354,856
(inc. VAT)
Add 10 units to get free delivery
Last RS stock
- Final 148 unit(s), ready to ship from another location
Units | Per unit | Per Pack* |
|---|---|---|
| 2 - 8 | R 154.285 | R 308.57 |
| 10 - 18 | R 150.43 | R 300.86 |
| 20 - 48 | R 145.915 | R 291.83 |
| 50 - 98 | R 140.08 | R 280.16 |
| 100 + | R 134.475 | R 268.95 |
*price indicative
- RS stock no.:
- 216-6206
- Mfr. Part No.:
- 8305AGLF
- Manufacturer:
- Renesas Electronics
Specification
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Width | 3.3 mm | |
| Length | 4mm | |
| Height | 0.9mm | |
| Series | 8305A | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Number of Outputs | 4 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Width 3.3 mm | ||
Length 4mm | ||
Height 0.9mm | ||
Series 8305A | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Number of Outputs 4 | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)